What it does

CFU Playground wraps the messy infrastructure of FPGA SoC design so you can focus on one thing: inventing new processor instructions that make ML inference faster. Pick a TFLite model, profile it layer by layer on an FPGA board (or in simulation), identify a bottleneck operator, design a small hardware “custom function unit” to replace it, and measure the cycle-count improvement. The loop is tight enough for multiple iterations per day.

The interesting bit

The project deliberately strips away demo polish — inputs are faked, outputs are just cycle counts — which keeps the feedback loop honest and fast. It’s performance engineering as a sport, not a product. The underlying stack is admirably open: LiteX for SoC assembly, VexRiscv for the RISC-V core, Amaranth for hardware description, with only Xilinx Vivado as the proprietary outlier.

Key highlights

• Supports multiple FPGA boards (Arty A7, iCEBreaker, Fomu, OrangeCrab, ULX3S, Nexys Video) via LiteX
• No hardware required: Renode simulation for functional testing, Verilator for cycle-accurate RTL sim
• Open-source toolchain options exist even for Xilinx parts (SymbiFlow/Conda) alongside vendor tools
• Template project structure (proj/proj_template) meant to be copied and hacked on
• Apache-2.0 licensed, though explicitly not an officially supported Google project

Caveats

• Linux-only host support (Debian/Ubuntu)
• Documentation is sparse; the README warns of “occasional breakage” and invites collaboration directly via email
• No pathway currently exists to export your optimized core into a real end-to-end demo

Verdict

Grab this if you’re a student, intern, or engineer who wants to learn processor microarchitecture by actually touching hardware and measuring results. Skip it if you need production-ready IP or a polished tutorial experience — the README is upfront that this is an “early prototype.”