An open-source ML GPU that refuses to run on an FPGA

What it does

VeriGPU is a from-scratch GPU design in SystemVerilog aimed at ASIC tape-out for machine learning. Its core uses a RISC-V-derived instruction set that gets rewritten wherever GPU semantics conflict with the base spec. The ambition is a lean accelerator built around BF16 arithmetic and a minimal set of ML-friendly float ops, exposed through a HIP-compatible API that could one day talk to PyTorch.

The interesting bit

The author deliberately shuns FPGA prototyping, arguing that FPGA-specific quirks would “taint” the design and make it fail to generalize to real silicon. That makes this a pure simulation play—verified in Verilator or Icarus—rather than a board you can flash.

Key highlights

• ISA is “loosely compliant” with RISC-V; the spec is broken wherever GPU design demands it
• Target is BF16 throughout, plus only the float ops that matter for ML: exp, log, tanh, sqrt
• Single-source C++ compilation lets you write host and device logic in one file
• Die area and timing are explicit optimization targets, with verification and metrics treated as first-class concerns
• Aimed at PyTorch compatibility via HIP, though SYCL or CUDA APIs are mentioned as possibilities

Caveats

• The README is largely aspirational (“Intend to,” “Hopefully”), so many features remain on the drawing board
• The demonstrated workload is a simple integer sum, far from proving out ML performance
• Deliberately no FPGA support, so validation is simulator-only unless another party funds a tape-out

Verdict

Hardware architects and ML systems researchers who enjoy gate-level reasoning will find this a refreshing change from black-box GPUs. If you need shipping silicon or a drop-in PyTorch backend today, this is not your project.