Google open-sources a RISC-V NPU for tiny wearables

What it does

Coral NPU is a hardware accelerator for machine-learning inference, delivered as open-source IP by Google Research. It is designed for integration into ultra-low-power SoCs targeting wearables such as hearables, augmented reality glasses, and smart watches. The core is built on the 32-bit RISC-V instruction set, so it avoids proprietary ISA lock-in.

The interesting bit

The design splits computation across three distinct processor components—matrix, vector SIMD, and scalar—using a four-stage pipeline that dispatches in-order but retires out-of-order. Rather than relying on cache, it uses small, single-cycle-latency SRAM scratchpads for instructions and data, which is the kind of unglamorous architectural choice that actually keeps power budgets intact in tiny devices.

Key highlights

• Open-source IP freely available for SoC integration
• 32-bit RISC-V base (RV32IMF_Zve32x) with 128-bit SIMD and a 256-bit pipeline on the roadmap
• Three-way compute: matrix, vector, and scalar units working together
• 8 KB instruction and 32 KB data tightly-coupled SRAM, presented as more efficient than cache
• AXI4 bus interfaces to interact with external memory and host CPUs
• Simulation and test targets included for Verilator and cocotb

Caveats

• Python 3.13 support is still in progress; the build flow currently requires 3.9–3.12
• The README omits synthesis metrics, power figures, and silicon status—how small and efficient it really is remains unstated

Verdict

Silicon teams building ultra-low-power edge devices should evaluate the datasheet. Software developers looking for a ready-made ML accelerator board should look elsewhere; this is IP, not a product.