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fengbintu/Neural-Networks-on-Silicon

A decade of AI chip papers, curated by someone who designs them

A living bibliography of neural-network accelerator research, maintained by an HKUST professor who actually builds the things.

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What it does This repository is a hand-curated reading list of conference papers on AI chips and deep-learning accelerators, spanning from 2014 through 2026. It is maintained by Fengbin Tu, an assistant professor at HKUST whose research focus is AI chip architecture. The collection covers major venues—ISSCC, ISCA, MICRO, HPCA, ASPLOS, DAC, FPGA, and others—with brief annotations on selected papers.

The interesting bit The curator is not a passive librarian. Tu’s own work appears in the list, and his annotations occasionally flag practical limitations (“the convolver can only support k=3”) or note when an idea was creative but not actually implemented in hardware. That practitioner skepticism is rare in academic reading lists.

Key highlights

  • Covers 12+ years of research across 10+ top-tier conferences
  • Includes foundational accelerators: DianNao, DaDianNao, Eyeriss, EIE, Cambricon
  • Annotations distinguish hardware generators from compiler frameworks from pure architecture proposals
  • Tracks evolution from FPGA prototypes through custom silicon to processing-in-memory and neuromorphic designs
  • Updated through 2026 (HPCA, ISSCC), suggesting active maintenance

Caveats

  • Coverage is explicitly personal—“papers that interest me”—so gaps are expected
  • Annotations are sparse and uneven; many papers get only a title and affiliation line
  • No search, no tagging, no PDF links: pure Markdown, so navigation is manual

Verdict Worth bookmarking if you are entering AI chip research or need a historical map of how we got from DianNao to today’s landscape. Skip it if you want systematic reviews, code, or tools—this is a bibliography with occasional marginalia, not a survey paper or framework.

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