divagr18/qwenputer
An experimental Qwen3.5-4B language model with a 32-bit RISC-V CPU compiled directly into its transformer weights, using the model's Gated DeltaNet state as RAM.
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Qwenputer modifies Qwen3.5-4B by compiling a 32-bit RISC-V CPU into the weights of 11 transformer layers, with those weights computed by a compiler rather than learned. The CPU uses the model’s Gated DeltaNet running state as RAM, storing code, data, registers, and a program counter there. It executes C and MicroPython code within the model’s forward passes and passes the official riscv-tests suites. Model variants are published on Hugging Face and ModelScope.
Frequently asked
- What is divagr18/qwenputer?
- An experimental Qwen3.5-4B language model with a 32-bit RISC-V CPU compiled directly into its transformer weights, using the model's Gated DeltaNet state as RAM.
- Is qwenputer open source?
- Yes — divagr18/qwenputer is an open-source project tracked on heatdrop.
- What language is qwenputer written in?
- divagr18/qwenputer is primarily written in Python.
- How popular is qwenputer?
- divagr18/qwenputer has 553 stars on GitHub.
- Where can I find qwenputer?
- divagr18/qwenputer is on GitHub at https://github.com/divagr18/qwenputer.